Phase locked loops (PLLs) are electronic circuits that have been used to generate output signals having a phase related to that of a reference input signal. PLLs have typically included a phase detector, a low pass filter, a variable frequency oscillator, and a feedback path. In traditional analog PLLs, the phase detector is an analog multiplier and the oscillator is a voltage controlled oscillator.
One of the limitations of traditional analog PLLs is that the input frequency must typically be at least higher than the bandwidth of the PLL. Typically, the input frequency must be at least five times higher than the bandwidth of the PLL in order to maintain output signal stability. As the reference frequency becomes smaller, the PLL bandwidth narrows to satisfy the stability criteria. The resistor and capacitor values of the low pass filter are then increased to accommodate the narrower PLL bandwidth. Smaller reference frequencies therefore require larger resistors and capacitors, which may not be practical to integrate. These limitations limit the use of analog PLLs in applications having a slow input reference clock frequency and a lack of space for larger external resistors or capacitors. These applications may include low power portable devices, such as battery operated mobile computing devices, smart phones, and electronics.
In general, an analog PLL is stable when the normalized loop gain (K) multiplied by the time constant of the loop filter zero (τz) is less than the following function of the angular frequency ƒ(ωin):
      K    ⁢                  ⁢          τ      2        <      1                  π                              ω            in                    ⁢                      τ            z                              ⁢              (                  1          +                      π                                          ω                in                            ⁢                              τ                z                                                    )            
To get around this stability restriction, manufacturers have included additional external passive signal conditioning elements, such as, for example, resistors and capacitors, to realize a narrow loop bandwidth in order for the PLL to lock to a low input frequency reference signal. Adding these additional external resistors and capacitors may increase the time constant τz since in some embodiments, τz=RzCc while K=IcpKoscRz/2πN, though in other embodiments, other functions may be used to calculate the time constant and/or normalized loop gain. However, these additional elements require additional space and have an added cost associated with a higher integrated circuit pin count. As portable computing and electronic devices get smaller, it is increasingly desirable to minimize circuit size and eliminate external elements.
Thus, there is a need for an analog PLL circuit that is able to process slower reference frequency input signals without the need for additional external signal conditioning elements, such as resistors and capacitors.